FIG. 17 is across-sectional view of a conventional trench gate power semiconductor device 900.
As shown in FIG. 17, the conventional trench gate power semiconductor device 900 is a trench gate power semiconductor device which includes an n+-type epitaxial layer 911 (not shown in the drawing) formed in the vicinity of a p-type semiconductor substrate 910 (not shown in the drawing) and a surface of the p-type semiconductor substrate 910, an n−-type epitaxial layer 912 (a semiconductor layer of first conductive type) arranged on the n+-type epitaxial layer 911, a p-type body region 920 (a body region of second conductive type) formed in the vicinity of an upper surface of the n−-type epitaxial layer 912, a plurality of trenches 914 formed such that the trenches 914 reach the n−-type epitaxial layer 912 from an upper surface side of the p-type body region 920, and gates 918 formed in the plurality of trenches 914 by way of gate insulation films 916. Emitter regions 922 are formed in the vicinity of an upper surface of the p-type body region 920 in an inter-trench region sandwiched between the trenches 914. An insulation layer 928 is formed over the trenches 914 and an emitter electrode 932 is formed over the insulation layer 928. Further, a cathode electrode 934 (not shown in the drawing) is formed over a lower surface of the p-type semiconductor substrate 910.
In the conventional trench gate power semiconductor device 900 having such a constitution, in a peripheral region GR which disposed further outside the outermost peripheral trench 914, a p-type semiconductor region 920a is formed such that the p-type semiconductor region 920a is connected to the p-type body region 920 and surrounds the p-type body region 920. The p-type semiconductor region 920a is formed deeper than the p-type body region 920 so as to maintain a high breakdown voltage thereof. The p-type semiconductor region 920a and the p-type body region 920 are connected to the emitter electrode 932 via contact holes CH formed in an upper surface of a side diffusion region SD and contact holes CH formed in an upper surface of a margin region MR adjacent to the side diffusion region SD. The emitter regions 922 are not formed on the upper surface of the margin region MR. Here, in FIG. 17, a symbol CR indicates a cell region.
Due to such constitution, according to the conventional trench gate power semiconductor device 900, most of the holes H generated in a relatively large quantity near the side diffusion region SD when a gate voltage is made to return from an ON voltage to an OFF voltage in the emitter electrode 932 pass through the side diffusion region SD and are collected by the emitter electrode 932 and hence, the holes can be speedily collected when the gate voltage is made to return to the OFF voltage thus accelerating a speed of the switching operation (for example, see patent document 1).    Patent document 1: Japan Published Unexamined Application No. Hei 9-270512 (FIG. 1 and FIG. 2)